To achieve a high-integrated nonvolatile memory operable at high speed, a phase change memory has continuously been developed. Such a phase change memory is described in Non-patent documents 1, 2, and 3 and Patent document 1. For example, the phase change memory of Non-patent document 1 stores information, by taking advantage of a characteristic that the resistance of a phase change material (a chalcogenide material) is changed in accordance with its state. An operation for writing the resistance of the phase change material is achieved when the state of the material is altered by heat of a current flowing thereto. To set a high resistance value (the memory is made amorphous), so-called a RESET operation, the memory is maintained at a relatively high temperature. To set a low resistance value (the memory is made crystallized), so-called a SET operation, the memory is maintained at a relatively low temperature for a sufficient period of time. For the phase change material, an operation for reading is executed by controlling a current to flow in such a range that the resistance of phase change material does not change.
Non-patent document 2 and Patent document 1 disclose the characteristic of the phase change resistance. Non-patent document 3 discloses a memory cell comprising the phase change resistance and an NMOS transistor.
Such documents disclose not only a high speed ROM (Read-Only Memory), but also the possibility of a nonvolatile RAM (Random Access Memory), and mention also realization of an integrated memory having both systems of ROM and RAM. In the phase change memory, if an electrode area is small in the phase change element, the phase of the element can be changed at a low voltage, thus easily realizing the scaling. Because the phase change resistance greatly changes, a read operation can be performed at a high speed. For these reasons, it is hoped that the high-speed nonvolatile memory will be realized using the phase change memory.    [Non-patent document 1] 2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 202–203.    [Non-patent document 2] 2002 IEEE International Electron Devices Meeting, Technical Digest, pp. 923–926.    [Non-patent document 3] 2003 Non-Volatile Semiconductor Memory Workshop, Digest of Technical Papers, pp. 91–92.    [Patent document 1] JP-A No. 100084/2003